This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-225523, filed on Aug. 2, 2002, the entire contents of which are incorporated herein by reference.
(1) Field of the Invention
The present invention relates to an apparatus and a method for calculating a simulation coverage, and more particularly to the apparatus and the method that are arranged to calculate a simulation coverage for a logic circuit through the use of a computer.
(2) Description of the Related Art
Today, the system LSI (Large Scale Integrated Circuit) has been made higher in function and greater in logical scale, so that the verification in designing such a system LSI may become longer and longer. For the design verification, as an index to a complete verification, a coverage is used.
The coverage is basically calculated on the basis of the number of lines executed by the design simulation, included in all lines described in a hardware description language (referred to as a HDL). This kind of coverage is called a line coverage.
However, the line coverage, that is, the conventional verifying method has no concept of time, concretely, no concept of when a certain line is executed. Hence, even though the line coverage ratio reaches 100%, disadvantageously, it does not necessarily mean the effective design verification.
Hereafter, this disadvantage will be concretely described.
FIG. 7 shows an exemplary description of a HDL.
Further, FIG. 8 is a circuit diagram showing a circuit designed in the HDL description shown in FIG. 7.
In FIG. 7 and FIG. 8, the block A described in the HDL corresponds to a circuit 50, the block B corresponds to a circuit 51, and the block C corresponds to a circuit 52, each of which circuits is composed of a flip-flop, for example.
Hereinafter, the description will be expanded along the case that the circuit shown in FIG. 8 is verified.
In FIG. 8, P, Q, EN, OUT, a, and b denote signal names, respectively.
Each of the blocks A, B and C includes a description of xe2x80x9calways @(posedge CLK) beginxe2x80x9d and is started on the rise of a clock signal (not shown). In the circuit 50 described in the block A, if P=1, a=a1 is outputted, while if not, a=a2 is outputted. In the circuit 51 described in the block B, if Q=1, b=b1 is outputted, while if not, b=b2 is outputted. Further, in the circuit 52 described in the block C, if EN=1, OUT=aandb is outputted, while if not, OUT=0 is outputted.
FIG. 9 shows test patterns that are effective in verifying the operation of the logic circuit shown in FIG. 8.
For the logic circuit shown in FIG. 8, four effective test patterns may be provided, that is, a pattern (1), a pattern (2), a pattern (3), and a pattern (4) as shown in FIG. 9, in which xe2x80x9c-xe2x80x9d indicates any value of 0 and 1.
Herein, the description will be oriented to the case that the following test patterns are entered by the user.
FIG. 10 shows an example of the test patterns entered by the user.
In a case that the user enters the patterns xcex1 and xcex2 for verifying the logic circuit shown in FIG. 8, the pattern xcex1 covers the lines (1) to (4) and (6) shown in FIG. 7, while the pattern xcex2 covers the lines (1) to (6) shown therein. It covers all lines. Although it means that only the pattern xcex2 is the effective one of the test patterns shown in FIG. 9, the resulting line coverage ratio reaches 100%. This is not the complete verification.
The present invention is made in consideration of the foregoing respect. It is an object of the present invention to provide a simulation coverage calculating apparatus that is arranged to calculate such a coverage as implementing a sufficient verification.
It is the other object of the present invention to provide a simulation coverage calculating method that is arranged to calculate such a coverage as implementing a sufficient verification.
In order to achieve the first object, the simulation coverage calculating apparatus is provided for calculating a simulation coverage for a logic circuit. The simulation coverage calculating apparatus includes a first input unit reading a property that represents one or more effective test patterns to the logic circuit to be verified; an effective test pattern calculating unit calculating one or more effective test patterns based on the property; a second input unit reading a test pattern entered and executed by a verifier; a coverage ratio calculating unit calculating a coverage ratio from the ratio of the number of the executed test patterns matched to the effective test patterns to the number of all the effective test patterns; and an output unit outputting the calculated coverage ratio.
In order to achieve the second object, the simulation coverage calculating method is provided for calculating a simulation coverage for a logic circuit through the use of a computer. The simulation coverage calculating method includes the steps of reading a property that represents one or more effective test patterns to the logic circuit to be verified; calculating the effective test patterns based on the property; reading one or more test patterns entered and executed by the verifier; and calculating a coverage ratio from a ratio of the number of the executed test patterns matched to the effective test patterns to the number of all the effective test patterns.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.